1. Field of the Invention
The present invention relates generally to electrical circuits and more particularly, but not exclusively, to quasi-resonant converters.
2. Description of the Background Art
A switched mode power supply (SMPS) includes a switch element (also known as a “primary switch”), such as a metal oxide semiconductor field effect transistor (MOSFET), to convert an alternating current (AC) source to a regulated DC output voltage. The switching of the switch element may be controlled by pulse width modulation (PWM) or other control scheme. An SMPS may include a converter that transforms a direct current (DC) voltage to another DC voltage. For example, an SMPS may include a quasi-resonant converter. In a typical quasi-resonant converter, the switch element is turned on when the voltage across the switch element is at its minimum at resonance, which is also referred to as the “valley”, to reduce switching loss.
U.S. Pat. No. 7,791,909, which is incorporated herein by reference in its entirety, discloses an example of a quasi-resonant converter that uses a MOSFET as the switch element. In the '909 patent, the MOSFET being used as the switch element is prohibited from being turned on during a blanking period TB (e.g., see FIG. 1A). After expiration of the banking period, the MOSFET is turned on when the valley of the drain-source voltage VDS of the MOSFET is detected within a timeout period. The MOSFET is forced to turn on if the valley is not detected within the timeout period. In this case, it may have higher switching loss due to potentially high VDS voltage across the MOSFET when the MOSFET is turned on, which is also referred to as “hard switching”.
The basic operation of the quasi-resonant converter of the '909 patent is illustrated in FIGS. 1A-1D. In FIGS. 1A-1D, the current IDS is the drain-source current of the MOSFET, VDS is the drain-source voltage of the MOSFET, TB is the blanking period, TS is the switching time, TW is the waiting period, and TSMAX is the timeout period. As shown in FIG. 1A, after the MOSFET is turned off, the MOSFET is not turned on until after the valley is detected after expiration of the blanking period. FIG. 1B illustrates a scenario where the valley is detected during the waiting period after one resonance cycle and FIG. 1C illustrates a scenario where the valley is detected during the waiting period within the first resonance cycle. FIG. 1D illustrates a scenario where the valley is not detected within the waiting period. In that scenario, the MOSFET is forced to turn on after expiration of the timeout period.
FIG. 2 shows plots of switching frequency versus output power in quasi-resonant converters with valley switching, such as in the '909 patent (see curve 210) and other quasi-resonant converters with valley switching (see curve 220). In the example of FIG. 2, the points A, B, C, and D correspond to the scenarios of FIGS. 1A, 1B, 1C, and 1D, respectively. Note the variation in switching frequency depending on when the valley is detected.
To ensure valley switching, the timeout period should be longer than the blanking period plus a resonance ring period. That is,TSMAX>TB+TRING where TSMAX is the timeout period, TB is the blanking period, and TRING is the resonance ring period. This results in relatively wide frequency variation (see FIG. 2), which is not desirable in applications that require a limited switching frequency range. Otherwise, the MOSFET is forced to be turned on when the timeout period expires, thereby causing hard switching and larger switching losses.